led_villog1s Project Status | |||
Project File: | led_villog1s.ise | Current State: | Placed and Routed |
Module Name: | villog1s |
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No Errors |
Target Device: | xc3s200-4ft256 |
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1 Warning |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
led_villog1s Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 33 | 3,840 | 1% | ||
Number of 4 input LUTs | 41 | 3,840 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 37 | 1,920 | 1% | ||
Number of Slices containing only related logic | 37 | 37 | 100% | ||
Number of Slices containing unrelated logic | 0 | 37 | 0% | ||
Total Number of 4 input LUTs | 72 | 3,840 | 1% | ||
Number used as logic | 41 | ||||
Number used as a route-thru | 31 | ||||
Number of bonded IOBs | 10 | 173 | 5% | ||
Number of BUFGMUXs | 1 | 8 | 12% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | K okt. 7 11:50:48 2008 | 0 | 1 Warning | 0 | |
Translation Report | Current | K okt. 7 11:59:28 2008 | 0 | 0 | 0 | |
Map Report | Current | K okt. 7 11:59:42 2008 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | K okt. 7 11:59:59 2008 | 0 | 0 | 2 Infos | |
Static Timing Report | Current | K okt. 7 12:00:07 2008 | 0 | 0 | 3 Infos | |
Bitgen Report |