labor1_4 Project Status
Project File: labor1_4.ise Current State: Programming File Generated
Module Name: dekad_kij
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
2 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
labor1_4 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 47 3,840 1%  
Number of 4 input LUTs 55 3,840 1%  
Logic Distribution     
Number of occupied Slices 46 1,920 2%  
    Number of Slices containing only related logic 46 46 100%  
    Number of Slices containing unrelated logic 0 46 0%  
Total Number of 4 input LUTs 86 3,840 2%  
    Number used as logic 55      
    Number used as a route-thru 31      
Number of bonded IOBs 30 173 17%  
Number of BUFGMUXs 1 8 12%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentCs okt. 9 09:00:28 200802 Warnings2 Infos
Translation ReportCurrentCs okt. 9 09:01:22 2008000
Map ReportCurrentCs okt. 9 09:01:26 2008002 Infos
Place and Route ReportCurrentCs okt. 9 09:01:36 2008003 Infos
Static Timing ReportCurrentCs okt. 9 09:01:38 2008003 Infos
Bitgen ReportCurrentCs okt. 9 09:01:46 2008001 Info

Date Generated: 11/19/2008 - 08:40:31