labor1_1 Project Status | |||
Project File: | labor1_1.ise | Current State: | Programming File Generated |
Module Name: | dekad_kij |
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No Errors |
Target Device: | xc3s200-4ft256 |
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No Warnings |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
labor1_1 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 7 | 3,840 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 4 | 1,920 | 1% | ||
Number of Slices containing only related logic | 4 | 4 | 100% | ||
Number of Slices containing unrelated logic | 0 | 4 | 0% | ||
Total Number of 4 input LUTs | 7 | 3,840 | 1% | ||
Number of bonded IOBs | 24 | 173 | 13% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sze okt. 8 11:23:24 2008 | 0 | 0 | 0 | |
Translation Report | Current | Sze okt. 8 11:37:45 2008 | 0 | 0 | 0 | |
Map Report | Current | Sze okt. 8 11:37:58 2008 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Sze okt. 8 11:38:09 2008 | 0 | 0 | 1 Info | |
Static Timing Report | Current | Sze okt. 8 11:38:16 2008 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Sze okt. 8 11:38:55 2008 | 0 | 0 | 1 Info |