labor1_4 Project Status | |||
Project File: | labor1_4.ise | Current State: | Programming File Generated |
Module Name: | dekad_kij |
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No Errors |
Target Device: | xc3s200-4ft256 |
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2 Warnings |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
labor1_4 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 47 | 3,840 | 1% | ||
Number of 4 input LUTs | 55 | 3,840 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 46 | 1,920 | 2% | ||
Number of Slices containing only related logic | 46 | 46 | 100% | ||
Number of Slices containing unrelated logic | 0 | 46 | 0% | ||
Total Number of 4 input LUTs | 86 | 3,840 | 2% | ||
Number used as logic | 55 | ||||
Number used as a route-thru | 31 | ||||
Number of bonded IOBs | 30 | 173 | 17% | ||
Number of BUFGMUXs | 1 | 8 | 12% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Cs okt. 9 09:00:28 2008 | 0 | 2 Warnings | 2 Infos | |
Translation Report | Current | Cs okt. 9 09:01:22 2008 | 0 | 0 | 0 | |
Map Report | Current | Cs okt. 9 09:01:26 2008 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Cs okt. 9 09:01:36 2008 | 0 | 0 | 3 Infos | |
Static Timing Report | Current | Cs okt. 9 09:01:38 2008 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Cs okt. 9 09:01:46 2008 | 0 | 0 | 1 Info |