labor1_3 Project Status | |||
Project File: | labor1_3.ise | Current State: | Programming File Generated |
Module Name: | dekad_kij |
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No Errors |
Target Device: | xc3s200-4ft256 |
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2 Warnings |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
labor1_3 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 33 | 3,840 | 1% | ||
Number of 4 input LUTs | 70 | 3,840 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 52 | 1,920 | 2% | ||
Number of Slices containing only related logic | 52 | 52 | 100% | ||
Number of Slices containing unrelated logic | 0 | 52 | 0% | ||
Total Number of 4 input LUTs | 102 | 3,840 | 2% | ||
Number used as logic | 70 | ||||
Number used as a route-thru | 32 | ||||
Number of bonded IOBs | 29 | 173 | 16% | ||
Number of BUFGMUXs | 1 | 8 | 12% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Cs okt. 9 10:00:32 2008 | 0 | 1 Warning | 0 | |
Translation Report | Current | Cs okt. 9 10:00:46 2008 | 0 | 0 | 0 | |
Map Report | Current | Cs okt. 9 10:00:52 2008 | 0 | 1 Warning | 4 Infos | |
Place and Route Report | Current | Cs okt. 9 10:01:02 2008 | 0 | 0 | 3 Infos | |
Static Timing Report | Current | Cs okt. 9 10:01:06 2008 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Cs okt. 9 10:01:12 2008 | 0 | 0 | 1 Info |