labor1_1 Project Status
Project File: labor1_1.ise Current State: Programming File Generated
Module Name: dekad_kij
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
No Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
labor1_1 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 3,840 1%  
Logic Distribution     
Number of occupied Slices 4 1,920 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 3,840 1%  
Number of bonded IOBs 24 173 13%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSze okt. 8 11:23:24 2008000
Translation ReportCurrentSze okt. 8 11:37:45 2008000
Map ReportCurrentSze okt. 8 11:37:58 2008002 Infos
Place and Route ReportCurrentSze okt. 8 11:38:09 2008001 Info
Static Timing ReportCurrentSze okt. 8 11:38:16 2008003 Infos
Bitgen ReportCurrentSze okt. 8 11:38:55 2008001 Info

Date Generated: 10/08/2008 - 17:39:29