Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:10.1 (WebPACK) Target Family: spartan3
OS Platform: NT Target Device:
Project ID (random number) 22203.4273.1 Target Package:
Registration ID 1BAYAJ9FAMJXSWSEX79WG338H Target Speed:
Date Generated K okt. 7 16:03:54 2008
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
ROMs=1
  • 16x8-bit ROM=1
Registers=1
  • Flip-Flops=1
Counters=1
  • 32-bit up counter=1
MiscellaneousStatistics
  • AGG_BONDED_IO=26
  • AGG_IO=26
  • AGG_SLICE=41
  • NUM_4_INPUT_LUT=79
  • NUM_BONDED_IOB=26
  • NUM_BUFGMUX=1
  • NUM_CYMUX=39
  • NUM_LUT_RT=31
  • NUM_SLICEL=41
  • NUM_SLICE_FF=33
  • NUM_XOR=31
NetStatistics
  • NumNets_Active=123
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=17
  • NumNodesOfType_Active_CNTRLPIN=18
  • NumNodesOfType_Active_DOUBLE=116
  • NumNodesOfType_Active_DUMMY=157
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_GLOBAL=12
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=184
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=80
  • NumNodesOfType_Active_OUTPUT=92
  • NumNodesOfType_Active_PREBXBY=1
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VUNIHEX=10
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=5
  • NumNodesOfType_Vcc_PREBXBY=1
  • NumNodesOfType_Vcc_VCCOUT=6
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=26
  • IOB_INBUF=6
  • IOB_OUTBUF=20
  • IOB_PAD=26
  • SLICEL=41
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=20
  • SLICEL_CYMUXG=19
  • SLICEL_F=39
  • SLICEL_FFX=16
  • SLICEL_FFY=17
  • SLICEL_G=40
  • SLICEL_GNDF=19
  • SLICEL_GNDG=19
  • SLICEL_XORF=15
  • SLICEL_XORG=16
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
IOB_PAD
  • DRIVEATTRBOX=[12:20]
  • IOATTRBOX=[LVCMOS25:26]
  • SLEW=[SLOW:20]
SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:16]
  • FFX_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SYNC_ATTR=[ASYNC:16]
SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:16] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SYNC_ATTR=[ASYNC:17]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=6
  • O1=20
  • PAD=26
IOB_INBUF
  • IN=6
  • OUT=6
IOB_OUTBUF
  • IN=20
  • OUT=20
IOB_PAD
  • PAD=26
SLICEL
  • BX=2
  • BY=1
  • CE=1
  • CIN=18
  • CLK=17
  • COUT=19
  • F1=39
  • F2=23
  • F3=7
  • F4=7
  • G1=40
  • G2=24
  • G3=8
  • G4=8
  • SR=17
  • X=18
  • XQ=16
  • Y=20
  • YQ=17
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=20
  • 1=20
  • OUT=20
  • S0=20
SLICEL_CYMUXG
  • 0=19
  • 1=19
  • OUT=19
  • S0=19
SLICEL_F
  • A1=39
  • A2=23
  • A3=7
  • A4=7
  • D=39
SLICEL_FFX
  • CK=16
  • D=16
  • Q=16
  • SR=16
SLICEL_FFY
  • CE=1
  • CK=17
  • D=17
  • Q=17
  • SR=17
SLICEL_G
  • A1=40
  • A2=24
  • A3=8
  • A4=8
  • D=40
SLICEL_GNDF
  • 0=19
SLICEL_GNDG
  • 0=19
SLICEL_XORF
  • 0=15
  • 1=15
  • O=15
SLICEL_XORG
  • 0=16
  • 1=16
  • O=16
 
Tool Usage
Command Line History
  • sch2verilog -intstyle ise -family spartan3 -w <ise_file> <fname>.vf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
bitgen 3 3 0 0 0 0 0
map 6 6 0 0 0 0 0
ngdbuild 15 15 0 0 0 0 0
par 6 6 0 0 0 0 0
trce 6 6 0 0 0 0 0
xst 15 15 0 0 0 0 0
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=Verilog
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_SCHEMATIC=1 FILE_UCF=1
FILE_VHDL=2 PROP_DevDevice=xc3s200
PROP_DevFamily=Spartan3 PROP_DevSpeed=-4
PROP_FitterReportFormat=HTML PROP_UserConstraintEditorPreference=Constraints Editor
Project duration(days)=0