demo_a Project Status
Project File: demo_a.ise Current State: Programming File Generated
Module Name: blokksema
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
1 Warning
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
demo_a Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 73 3,840 1%  
Number of 4 input LUTs 111 3,840 2%  
Logic Distribution     
Number of occupied Slices 93 1,920 4%  
    Number of Slices containing only related logic 93 93 100%  
    Number of Slices containing unrelated logic 0 93 0%  
Total Number 4 input LUTs 180 3,840 4%  
Number used as logic 111      
Number used as a route-thru 69      
Number of bonded IOBs 16 173 9%  
    IOB Flip Flops 1      
Number of GCLKs 1 8 12%  
Total equivalent gate count for design 1,983      
Additional JTAG gate count for IOBs 768      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentP nov. 17 13:15:08 200601 Warning1 Info
Translation ReportCurrentP nov. 17 13:15:20 2006000
Map ReportCurrentP nov. 17 13:15:30 2006003 Infos
Place and Route ReportCurrentP nov. 17 13:15:44 2006002 Infos
Static Timing ReportCurrentP nov. 17 13:15:50 2006002 Infos
Bitgen ReportCurrentP nov. 17 13:16:00 2006000
 
Secondary Reports [-]
Report NameStatusGenerated
Xplorer Report  

Date Generated: 11/19/2008 - 23:30:14