demo_a Project Status | |||
Project File: | demo_a.ise | Current State: | Programming File Generated |
Module Name: | blokksema |
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No Errors |
Target Device: | xc3s200-4ft256 |
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1 Warning |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
demo_a Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 73 | 3,840 | 1% | ||
Number of 4 input LUTs | 111 | 3,840 | 2% | ||
Logic Distribution | |||||
Number of occupied Slices | 93 | 1,920 | 4% | ||
Number of Slices containing only related logic | 93 | 93 | 100% | ||
Number of Slices containing unrelated logic | 0 | 93 | 0% | ||
Total Number 4 input LUTs | 180 | 3,840 | 4% | ||
Number used as logic | 111 | ||||
Number used as a route-thru | 69 | ||||
Number of bonded IOBs | 16 | 173 | 9% | ||
IOB Flip Flops | 1 | ||||
Number of GCLKs | 1 | 8 | 12% | ||
Total equivalent gate count for design | 1,983 | ||||
Additional JTAG gate count for IOBs | 768 |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | P nov. 17 13:15:08 2006 | 0 | 1 Warning | 1 Info | |
Translation Report | Current | P nov. 17 13:15:20 2006 | 0 | 0 | 0 | |
Map Report | Current | P nov. 17 13:15:30 2006 | 0 | 0 | 3 Infos | |
Place and Route Report | Current | P nov. 17 13:15:44 2006 | 0 | 0 | 2 Infos | |
Static Timing Report | Current | P nov. 17 13:15:50 2006 | 0 | 0 | 2 Infos | |
Bitgen Report | Current | P nov. 17 13:16:00 2006 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Xplorer Report |