labor1_2 Project Status
Project File: labor1_2.ise Current State: Placed and Routed
Module Name: dekad_kij
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
No Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
labor1_2 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 33 3,840 1%  
Number of 4 input LUTs 48 3,840 1%  
Logic Distribution     
Number of occupied Slices 41 1,920 2%  
    Number of Slices containing only related logic 41 41 100%  
    Number of Slices containing unrelated logic 0 41 0%  
Total Number of 4 input LUTs 79 3,840 2%  
    Number used as logic 48      
    Number used as a route-thru 31      
Number of bonded IOBs 26 173 15%  
Number of BUFGMUXs 1 8 12%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSze okt. 8 12:00:51 2008000
Translation ReportCurrentSze okt. 8 12:01:06 2008000
Map ReportCurrentSze okt. 8 12:01:15 2008002 Infos
Place and Route ReportCurrentSze okt. 8 12:01:30 2008003 Infos
Static Timing ReportCurrentSze okt. 8 12:01:37 2008003 Infos
Bitgen ReportOut of DateK okt. 7 15:42:18 2008001 Info

Date Generated: 10/08/2008 - 20:06:23