labor1_3 Project Status
Project File: labor1_3.ise Current State: Programming File Generated
Module Name: dekad_kij
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
2 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
labor1_3 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 33 3,840 1%  
Number of 4 input LUTs 70 3,840 1%  
Logic Distribution     
Number of occupied Slices 52 1,920 2%  
    Number of Slices containing only related logic 52 52 100%  
    Number of Slices containing unrelated logic 0 52 0%  
Total Number of 4 input LUTs 102 3,840 2%  
    Number used as logic 70      
    Number used as a route-thru 32      
Number of bonded IOBs 29 173 16%  
Number of BUFGMUXs 1 8 12%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentCs okt. 9 10:00:32 200801 Warning0
Translation ReportCurrentCs okt. 9 10:00:46 2008000
Map ReportCurrentCs okt. 9 10:00:52 200801 Warning4 Infos
Place and Route ReportCurrentCs okt. 9 10:01:02 2008003 Infos
Static Timing ReportCurrentCs okt. 9 10:01:06 2008003 Infos
Bitgen ReportCurrentCs okt. 9 10:01:12 2008001 Info

Date Generated: 10/09/2008 - 20:51:06