cshazi Project Status (11/24/2010 - 02:33:07)
Project File: cshazi.xise Parser Errors: No Errors
Module Name: cshazi Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 6 4,896 1%  
Number of 4 input LUTs 7 4,896 1%  
Number of occupied Slices 4 2,448 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 4,896 1%  
Number of bonded IOBs 16 108 14%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.80      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSze nov. 24 02:31:55 2010000
Translation ReportCurrentSze nov. 24 02:32:04 2010000
Map ReportCurrentSze nov. 24 02:32:14 2010002 Infos (0 new)
Place and Route ReportCurrentSze nov. 24 02:32:52 2010003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSze nov. 24 02:32:57 2010005 Infos (0 new)
Bitgen ReportCurrentSze nov. 24 02:33:07 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentSze nov. 24 02:33:07 2010

Date Generated: 11/24/2010 - 02:33:07