Hazi_feladat_potzh Project Status | |||
Project File: | Hazi_feladat_potzh.xise | Parser Errors: | No Errors |
Module Name: | Hazi_feladat_potzh | Implementation State: | Placed and Routed |
Target Device: | xc3s100e-4tq144 |
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No Errors |
Product Version: | ISE 12.2 |
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No Warnings |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 6 | 1,920 | 1% | ||
Number of 4 input LUTs | 7 | 1,920 | 1% | ||
Number of occupied Slices | 4 | 960 | 1% | ||
Number of Slices containing only related logic | 4 | 4 | 100% | ||
Number of Slices containing unrelated logic | 0 | 4 | 0% | ||
Total Number of 4 input LUTs | 7 | 1,920 | 1% | ||
Number of bonded IOBs | 16 | 108 | 14% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.80 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sze nov. 24 18:30:48 2010 | 0 | 0 | 0 | |
Translation Report | Current | Sze nov. 24 18:31:10 2010 | 0 | 0 | 0 | |
Map Report | Current | Sze nov. 24 18:31:13 2010 | 0 | 0 | 2 Infos (0 new) | |
Place and Route Report | Current | Sze nov. 24 18:31:23 2010 | 0 | 0 | 3 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sze nov. 24 18:31:25 2010 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |